Ofertes de projectes

Virtual reality is becoming a tool for helping patients with several illnesses (strokes, frozen shoulder...) to engage in the rehabilitation exercises.

The purpose of this project is the creation of a serious game that helps patients to engage in rehabilitation exercises for the frozen shoulder.

If you are interested, do not hesitate to ask for more information. But please, before doing so, check my "Prospective students" tab on my webpage.

A common trait of current computing systems is that their internal data communication has become a fundamental bottleneck. Traditional interconnects are insufficient and threatening to halt progress unless fast and versatile communication alternatives are developed.

In the NaNoNetworking Center in Catalunya (N3Cat, www.n3cat.upc.edu), we are investigating the use of ultra-short range wireless communications an alternative to current interconnects. In our EU project EWiC, we aim to emulate chip-to-chip wireless communications within a computer. For that, we will emulate the behavior of a multi-chip CPU with FPGAs, and connect them wirelessly using Software-Defined Radios (SDR). 

N3Cat is looking for students wanting to acquire hands-on experience in the programming and interconnection of FPGAs, and to participate in a cutting-edge project to interconnect these FPGAs wirelessly. In more detail, the objectives of the thesis are:

- To help establishing the emulator and be able to simulate its behavior.
- To work in the implementation of adequate communication protocols for the integration of wireless interconnects in the emulated multi-FPGA system.
- To assess the performance of the system via measurement campaigns.

This Bachelor Thesis will take place at the Departament d'Arquitectura de Computadors (DAC) in collaboration with the STAR group at the Barcelona Supercomputing Center (BSC).

The System Tools and Advanced Runtimes (STAR) group at BSC focuses on research crossing multiple software layers from OS, runtimes, and low-level APIs, to programming models, tools, and applications. We run traditional HPC, AI, and Data Analytics applications on massively parallel HPC and Cloud platforms.

Arithmetic operations derived from stencils calculations often benefit from compiler optimisations and automatic vectorisation in the cases where the compiler has enough information and the data structures are adequately aligned and traversed.  While classical applications rely on double precision arithmetic operations with 64-bit floating-point precision, CPU manufacturers have recently begun introducing native hardware support down to 16-bit precision. 

The student will be tasked to adapt single-precision computational kernels of a variety of applications including, for example, the N-body problem, the heat equation, and some computational stencil used in computational fluid dynamics problems to their mixed-precision counterparts. Next, he or she will vectorise the kernels with the aid of OpenMP pragma directives and identify other optimisation opportunities like loop unrolling or cache blocking.  Finally, the student will asses the effects of mixed-precision and, in particular, any potential accuracy losses. 

The student will have the support from researchers within the STAR group, which will provide them guidance throughout the duration of the thesis.  The GTP models will be evaluated using the computational resources of our group.

This Bachelor Thesis will take place at the Departament d'Arquitectura de Computadors (DAC) in collaboration with the STAR group at the Barcelona Supercomputing Center (BSC).

The System Tools and Advanced Runtimes (STAR) group at BSC focuses on research crossing multiple software layers from OS, runtimes, and low-level APIs, to programming models, tools, and applications. We run traditional HPC, AI, and Data Analytics applications on massively parallel HPC and Cloud platforms.

Some popular iterative methods employed in the numerical resolution of sparse linear systems of equations are the Jacobi and Gauss¿Seidel (GS) algorithms. These techniques are often combined with more sophisticated Krylov subspace methods (KVMs) such as the conjugate gradient (CG) and the biconjugate gradient stabilized (BiCGStab) algorithms. These KVMs rely primarily on sparse matrix-vector (SpMV) calculations and can achieve better convergence rates than Jacobi and Gauss¿Seidel.

The student will be tasked to adapt several sparse matrix encodings for the SpMV operation. These formats include: coordinate format (COO), compressed row storage (CRS), lower-diagonal-upper (LDU), modified sparse row (MSR), lower-diagonal-upper (LDU), and lower-diagonal-upper CSR (LDUCSR). Next, he or she will evaluate various iterative methods on both CPU and GPU architectures. Finally, the student will asses the advantages and disadvantages of the encodings for each particular architecture.

The student will have the support from researchers within the STAR group, which will provide them guidance throughout the duration of the thesis. The iterative methods will be evaluated using the computational resources of our group.

This Bachelor Thesis will take place at the Departament d'Arquitectura de Computadors (DAC) in collaboration with the STAR group at the Barcelona Supercomputing Center (BSC).

The System Tools and Advanced Runtimes (STAR) group at BSC focuses on research crossing multiple software layers, from OS, runtimes, and low-level APIs, to programming models, tools, and applications. We run traditional HPC, AI, and Data Analytics applications on massively parallel HPC and Cloud platforms.

Machine learning (ML) has experienced a sustainable growth during the last decade and more lately with the emergence of LLMs driven almost exclusively by industry corporations. The size of such models is currently one of the major limitations to deploy them on resource-constrained environments. CPU manufacturers have begun introducing new hardware extensions such as VNNI and AMX in order to accelerate mixed-precision calculations during ML training and inference of low-bit precision LLMs.

The student will be tasked to quantise an already existing pretraining code and measure the gains in performance as well as the potential issues like accuracy losses. Next, he or she will optimize some of the most time-consuming kernels by relying upon optimised third-party libraries. Several LLMs will be analysed and compared, including some GPU implementations.

The student will have the support from researchers within the STAR group, which will provide them guidance throughout the duration of the thesis. The GTP models will be evaluated using the computational resources of our group.

Recent advancements in nanotechnology have enabled the development of means for sensing and wireless communications with unprecedented miniaturization and capabilities, to the point that they can be introduced into the gastrointestinal tract inside a pill or into the bloodstream in the form of passively flowing nanomachines. 

This opens the door to the idea of intra-body communication networks, this is, a swarm of nanosensors inside the human body that use communications to coordinate their actions to sense and localize specific events (lack of oxygen, biomarkers, etc). This can lead to the development of applications such as continuous monitoring of diabetes, detection and localization of cancer micro-tumors, or early detection of blood clots. These possibilities are currently investigated by our team at the N3Cat (www.n3cat.upc.edu).

In this context, We are looking for excellent and self-motivated individuals who are eager to develop ideas that will have a positive societal or socio-economic impact. In particular, the students will work on ONE of the following areas:

• Developing means of zero-power communications between nanosensors inside the human body.
• Designing protocols for communications from nanomachines inside the human body and implants or antennas in the skin surface.
• Studying mobility inside the gastrointestinal tract and human bloodstream towards creating mobility models for accurate simulation of intra-body communications.
• Dimensioning the system (inferring the required nanomachine density) to achieve a particular sensing goal/application.
• Developing AI schemes for the localization of events inside of the human body.

Seeing that not all neural networks fit to all problems, and that relational data is present in a wide variety of aspects of our daily life, the main focus of this thesis in N3Cat (www.n3cat.upc.edu) and BNN-UPC (www.bnn.upc.edu) is to explore the possibilities of the Graph Neural Networks (GNNs), whose aim is to learn and model graph-structured relational data. We are looking for students willing to study the uses, architectures, and algorithms of GNNs. To this end, the candidate will work on ONE of the following areas:

• Uses: Applying GNNs in emerging application areas, including but not limited to (1) electroencephalogram (EEG) analysis for Alzheimer's disease detection, epilepsy classification, motor imagery; (2) acceleration of the compilation of quantum computing algorithms
• Architectures: Investigating ways to accelerate the processing of GNNs in multiple computing platforms (CPU, GPU, accelerators).
• Algorithms: Developing meta-learning data-driven models to estimate the accuracy of a GNN for a given graph, without training, through synthetic graph generation and correlation analysis.

Gradient descend based RBM learning [1] is a computationally expensive procedure that requires the computation of a probability normalization constant (called the Partition function) that involves the computation of an exponentially large number of terms. In order to bypass that, different approximations exist, the most celebrated one being the Annealed Importance Sampling algorithm [2], that can be parallelized in one of its dimensions.

The goal of this project ir to implement the Annealed Importance Sampling for Restricted Boltzmann Machine (RBM) using python/CUDA, and compare the performance against a standard CPU implementation.

[1] "Training restricted Boltzmann machines: An introduction",
Asja Fischer and Christian Igel, Pattern Recognition 47, 25-39 (2014).

[2] "Annealed Importance Sampling", Radford M. Neal, Statistics and Computing 11, 125-139 (2001).

In today's digital landscape, the integration of AI and Big Data technologies has become essential for enhancing cyber-resilience for large and small companies. As cyber threats become more and more sophisticated, leveraging those advanced technologies is a must to protect sensitive information and make sure businesses can operate without disruption.

This internship offers a unique opportunity to work at the intersection of all those topics: AI, Big Data, and Cybersecurity. You will join an experienced team of data engineers and data scientists, and you will have the chance to build your own AI models for innovative cybersecurity products. You will also be analyzing and processing large amounts of data and have the opportunity to work with cross-functional teams within the Security Operations Center to integrate these advanced solutions into our SOAR system (Security Orchestration, Automation, and Response).

Computing systems are ubiquitous in our daily life and have transformed the way we learn, work, or communicate with each other, to the point that progress is intimately tied to the improvements brought by new generations of the processors that lie at the heart of these systems. 

A common trait of current computing systems is that their internal data communication has become a fundamental bottleneck. Traditional interconnects are insufficient and threatening to halt progress unless fast and versatile communication alternatives are developed.

In the NaNoNetworking Center in Catalunya (N3Cat, www.n3cat.upc.edu), we envisage a revolution in computer architecture enabled by the use of wireless communications (and other unconventional interconnect technologies) inside computer chips, both classical and quantum. Of course, this vision comes with its own set of challenges since we need to figure out the best way to architect these systems with the new capabilities of the interconnects. In this direction, the candidate will work on one of the following areas:

• Analysis of the communications workload in nowadays computer chips and development of network-on-chip architectures to serve such traffic optimally.
• Development of chiplet-based architectures in the classical domain in cache-coherent based systems, delving into the cache coherence protocol and the interface with the wireless interconnect.
• Development of a supercomputer-in-a-package, a chiplet-based architecture based on message passing, delving into how to speed up the MPI primitives with wireless communications.
• Study of scalable quantum computing systems enabled by wireless classical communication across the chips of the quantum computer and inside a cryogenic refrigerator.

Quantum computers promise exponential improvements over conventional ones due to the extraordinary properties of qubits. However, a quantum computer faces many challenges relative to the movement of qubits which is completely different from the movement of classical data. This thesis delves into these challenges and proposes solutions to create scalable quantum computers enabled by quantum communications, following the current European projects at N3Cat (www.n3cat.upc.edu) on scalable quantum computing.

The interested candidate will work in a group of several PhD students and in collaboration with Universitat Politècnica de València, working in ONE of the following areas:

• Designing classical (bit) and quantum (qubit) communication protocols and network architectures for communications inside a quantum computer.
• Assisting in the modeling of quantum short-range communications within our simulation framework, which is based on NetSquid.
• Developing qubit mapping, partitioning, and routing for scalable quantum computers.
• Study the use of AI to model quantum computers or develop qubit mapping and routing schemes.
• Study the potential adaptation of the existing quantum computing architectures to specific quantum machine learning algorithms (QAOA, VQE, others)

L'aplicació es desenvoluparà com a projecte pilot amb la voluntat de ser utilitzada per institucions educatives de Catalunya i estarà disponible en català i castellà.

L'estudiant col·laborarà en les tasques de definició funcional, disseny d'interfície i desenvolupament tècnic de la app, així com en la integració de continguts educatius facilitats per l'IDHC.

Hi ha finançament per remunerar l'execució del projecte.

Requisits mínims per a l'estudiant:
  · Coneixements bàsics de desenvolupament d'aplicacions mòbils (Android o multiplataforma com Flutter o Godot).
  · Familiaritat amb disseny d'interfícies d'usuari (UX/UI).
  · Capacitat per treballar en equip i comunicar-se amb perfils no tècnics.
  · Interès en temes socials, drets humans o sostenibilitat (valorat).
  · Es valorarà experiència prèvia amb jocs o aplicacions interactives.