Seminars of Innovation and Research in Informatics

The Xilinx Open Hardware Design Competition 2021 (http://www.openhw.eu/), is a multi-month competition for open source hardware designs, organised by Xilinx. The submitted project has to be ported on Xilinx toolchains and FPGAs.There are 3 categories (PhD/graduate, PYNQ and Compute Acceleration). The first one can be a Master or PhD thesis, or any other project developed while the student is enrolled in the Master or PhD program. For the PYNQ category the project can be implemented in Python or can be a parametrised Python overlay to allow someone to use it from Python, or simply a Verilog/VHDL project ported to the PYNQ Xilinx board. In the Compute Accelerator Category, the project has to use Alveo, a high-performance Xilinx FPGA which is designed to fit in servers and its programmed/used like a GPU, eg. using OpenCL and high-level compute libraries from Xilinx like BLAS. Alternatively, another scientific library can be ported/implemented as a project. Example projects from last year's entries can be found in http://www.openhw.eu/2020-results.html and the rules at http://www.openhw.eu/rules.html.

Self paced project development

The Technical University of Darmstadt announces the 2021 edition of INSPIRED, the International Project Week for Interdisciplinary Research-Oriented Digital Learning. This is an initiative of TU Darmstadt in the framework of the Euroepan University "UNITE!(open in new window)", in which UPC also participates. The 2021 program will be conducted in collaboration with the European Space Operations Center (ESOC) to develop the concept of " Extraterrestrial Greenhouse: Diving into an Multidisciplinary Toolbox to Challenge Gravity and Ensure Sustainability in Offshore Travel and Space Exploration". Because of the COVID-19 pandemic, this year's edition will be entirely ONLINE. *Warning:* Until January 31, 2021 on the INSPIRED website. A letter of motivation and academic transcripts are required. UPC students are UNITE students (full scholarship)

The PUMPS Summer School is delivered by the GPU Center of Excellence (GCOE) awarded by NVIDIA to the Barcelona Supercomputing Center (BSC) in association with Universitat Politècnica de Catalunya (UPC). This eighth edition of the Programming and Tuning Massively Parallel Systems summer school (PUMPS) is aimed at enriching the skills of researchers, graduate students and teachers with cutting-edge technique and hands-on experience in developing applications for many-core processors with massively parallel computing resources like GPU accelerators.

A week long interactive, and competitive, hackathon addressing HPC application porting and optimizing in the cloud, organised by the Arm HPC User Group (AHUG) in collaboration with Arm and AWS. Teams up to 4 people will undertake application porting and performance tuning of key HPC applications using virtual clusters on the AWS cloud ¿ powered by their Arm Neoverse-N1 based Graviton2 processor. Using the Spack package manager teams will have to control the installation of their codes ¿ and tune compiler, library and optimization flag choice to ensure a robust and performance tuned installation. Teams must then undertake performance and scalability studies and to compare against other processor architectures. Amassing points for successful builds, tests, performance analysis and tuning ¿ the team with the most points will take the prizes. Each team will have its own pre-built AWS clusters with Graviton2 c6gn EC2 instances and with x86-based instances for comparing results. Contributions that focus on getting a code to build and run successfully will count towards the goal as they will push the community forward. However, it's what you do to utilize the hardware to extract performance that will make the most difference for your team. The Graviton2 instances all have 64 cores per node, dual SIMD 128-bit units, and over 200 GB/s of peak memory bandwidth. They also have 100 Gbit/s networking with the Elastic Fabric Adapter (EFA) to support efficient MPI communications. The pre-built AWS clusters will come with ready-to-use development tools and optimized libraries from Arm and others for porting, running, and benchmarking the selected code(s). Teams will need to provide realistic inputs and data for test cases, and measure how a code performs in both single-node and multiple-node runs. Points will be awarded for every successful code-build and test case, and the number of points earned will increase for performance improvements. Spack recipe improvements will go upstream, and test-cases and workloads will go to a public GitHub repo where all the artifacts will get a DOI so you can reference them in a paper. Teams will also be assigned a mentor, and have guidance from a community of technology specialists from within AWS and Arm to enable them to get the most out of this experience.

Daily participation

HackUPC is the first student hackathon in Spain. Once a year, we aim to provide a space for students of all experience levels from all around the world where they can improve and learn new skills, meet awesome people and overall, have a great experience! This year's edition the hackathon will be held online.

We learnt how to use the AMD Hipify tools to convert CUDA codes to HIP. They were introduced to the AMD architecture, issues that could arise from the code conversion and the differences between CUDA and HIP.

All human activities have implications on our society. Professional exercise in engineering, being a researcher or running innovation projects imply making decisions that are not exclusively technical, they involve ethical considerations. Theoretical sessions are complemented with numerous examples and cases.

Friday: 11:00-13:00

The CUDA computing platform enables the acceleration of CPU-only applications to run on the world's fastest massively parallel GPUs. Experience C/C++ application acceleration by: Accelerating CPU-only applications to run their latent parallelism on GPUs Utilizing essential CUDA memory management techniques to optimize accelerated applications Exposing accelerated application potential for concurrency and exploiting it with CUDA streams Leveraging command line and visual profiling to guide and check your work Upon completion, you'll be able to accelerate and optimize existing C/C++ CPU-only applications using the most essential CUDA tools and techniques. You'll understand an iterative style of CUDA development that will allow you to ship accelerated applications fast

Big data for social and economic sciences are described. GED distribution and Lp-Norm estimators are applied by using RStudio

16:000-20:00

The objective of this course is to learn how to use systems with more than one memory subsystem. We will see the different options on using Intel's KNL memory subsystems and systems equipped with Intel's Optane technology.

09:00-17:30

Lambda Days is a place where academia meets industry, where research and practical application collide. 2021 Lambda Days goes virtual but also becomes a fundraiser. Once again we join forces with Trends in Functional Programming (TFP) and Trends in Functional Programming in Education (TFPiE) so that for four days you can be at the centre of the functional programming world. Find out what is possible with functional programming - explore the latest in battle-tested Scala, Erlang and Haskell, experience the energy F# and Elixir bring to the table, connect with the innovators working with Elm, Luna and Ocaml, see what comes up next!

12:00 to 18:00

Lambda Days is a place where academia meets industry, where research and practical application collide. 2021 Lambda Days goes virtual but also becomes a fundraiser. Once again we join forces with Trends in Functional Programming (TFP) and Trends in Functional Programming in Education (TFPiE) so that for four days you can be at the centre of the functional programming world. Find out what is possible with functional programming - explore the latest in battle-tested Scala, Erlang and Haskell, experience the energy F# and Elixir bring to the table, connect with the innovators working with Elm, Luna and Ocaml, see what comes up next!

12:00 to 18:00

I have completed the course online through coursera.Here is the certificate https://www.coursera.org/account/accomplishments/verify/33VT29CE29MT and here are my solutions https://github.com/h0lyalg0rithm/fundamentals-intel-parallelism

This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now. You will need to purchase a DE10-Lite development kit. You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder. You will: Design and test a Binary Coded Decimal Adder. Design and test a PWM Circuit, with verification by simulation. Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design. Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file. Compile your completed hardware using Quartus Prime. Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse. Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT. Compile your completed software using the SBT. Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. Record all your observations in a lab notebook pdf. Submit your project files and lab notebook for grading. This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.

The course brings together key information technologies used in manipulating, storing and analysing data including: basic tools for statistical analysis, techniques for parallel processing, tools for access to unstructured data, and storage solutions.

09:30-18:00

Embedded Software and Hardware Architecture

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder's Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

Objectives: The objective of this course is to give an overview of BSC storage solutions, Hecuba and dataClay. These two platforms allow to easily store and manipulate distributed data from object-oriented applications, enabling programmers to handle object persistence using the same classes they use in their programs, thus avoiding time consuming transformations between persistent and non-persistent data models. Also, Hecuba and dataClay enable programmers to transparently manage distributed data, without worrying about its location. This is achieved by adding a minimal set of annotations in the classes. Learning Outcomes In the course, the Hecuba and dataClay syntax, programming methodology and an overview of their internals will be given. Also, an overview of COMPSs at user level will be provided in order to take advantage of the distribution of data with both platforms. The attendees will get a first lesson about programming with the common storage interface that will enable them to start programming with both frameworks. A hands-on with simple introductory exercises will be also performed for each platform, with and without COMPSs to distribute the computation. The students who finish this course will be able to develop simple Hecuba and dataClay applications and to run them both in a local resource and in a distributed platform (initially in a private cloud)

10:00 - 18:00

This course will introduce you to the multiple forms of parallelism found in modern Intel architecture processors and teach you the programming frameworks for handling this parallelism in applications. You will get access to a cluster of modern manycore processors (Intel Xeon Phi architecture) for experiments with graded programming exercises. This course can apply to various HPC and datacenter workloads and framework including artificial intelligence (AI). You will learn how to handle data parallelism with vector instructions, task parallelism in shared memory with threads, parallelism in distributed memory with message passing, and memory architecture parallelism with optimized data containers. This knowledge will help you to accelerate computational applications by orders of magnitude, all the while keeping your code portable and future-proof.

Create a Nios II softcore processor hardware design using the Altera development flow Understand the benefits and steps of implementation of a custom instruction in the Nios II soft processor. List the types of IP available for FPGAs Use simulation with ModelSim to verify an FPGA Design

This course can also be taken for academic credit as ECEA 5360, part of CU Boulder?s Master of Science in Electrical Engineering degree. Programmable Logic has become more and more common as a core technology used to build electronic systems. By integrating soft-core or hardcore processors, these devices have become complete systems on a chip, steadily displacing general purpose processors and ASICs. In particular, high performance systems are now almost always implemented with FPGAs. This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. You use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or an engineer looking at a career change, this is a great course to enhance your career opportunities.

El curso enseña a programar mediante cuda en multigpus y solapando la transferencia de datos y el computo de ellos en las diversas gpus mediante streams.

Be careful: Places limited! An introduction to FPGA and Zynq technology will be covered including the PYNQ framework, along with some hands-on tutorials and examples on local hardware (provided by the Xilinx University Program to each attendee). The Xilinx Vitis software development environment for designing FPGA accelerators will be introduced. Vitis supports OpenCL, C and C++. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries. Participants will devise and build their own custom accelerators targeting Alveo and AWS F1 instances. Students can follow the guidance of the instructors to build custom designs from available open source libraries or to create their own custom accelerator design. The school will also include invited presentations from speakers at ETH and Xilinx on relevant topics, including an overview of the XACC program and the XACC at ETH Zurich.

9-18h

This year bitsxlaMarató, a hackathon for contributing to La Marató de TV3, a public Catalan charity effort, is organised by the Barcelona School of Informatics (FIB), Hackers@upc (organisers of HackUPC) and the Barcelona Supercomputing Center-Centro Nacional de Supercomputación (BSC), which come together to fight COVID-19. After a first edition focused on rare diseases, we are joining forces to stop the effects of COVID-19. Full of creativity, health and technology, where teachers, researchers and any professional from the fields of health and technology (but also from other areas!) will work as a team, for 3 days in a row, online. Together, they will develop and look for solutions to face all the challenges posed by COVID-19. This Marathon concerns everyone! Do not even think about missing it! The Hackathon will include training talks that are a must to attend! Besides, we hope to have very interesting guided activities! During the last day of the Hackathon, the teams will make the presentations and demonstrations of the solutions as well as proposals for solutions obtained to the challenges set out the first day. Now listen up! There will be (symbolic) prizes! In addition, a prize for the best project as well!, even though all the solutions and donations for the TV3 Marathon will be prizes by themselves for the millions of people affected! All of them will be grateful for it!

Friday (17-21:00h), Saturday (9-22h), Sunday (9-17h)

This hackathon targets application developers that are interested in investigating the impact of novel SVE extensions in their HPC applications.

The RISC-V Summit is the annual conference organised by the RISC-V Foundation, featuring 3 days of keynotes, technical talks and tutorials in addition to networking opportunities. In this year's event which will take place online, there are 3 speakers from UPC/BSC: Leonidas Kosmidis, Roger Espasa, Jaume Abella. Registration is free for students, using the UPC email address to obtain the "All Access Pass-Student" ticket from https://tmt.knect365.com/risc-v-summit/plan-your-visit/

18:00-2:00

All human activities have implications on our society. Research activity not only does but also the overall research system is based on trust. Then, responsible research conduct is of outmost importance. The goal of the course is to provide an overview of the rules and professional practices that are considered as responsible conduct of research and engineering. Ph. D. students, post-doctoral researchers and everybody involved in research and innovation must know the principles and practices that define a responsible conduct and the ones that are not appropriate and are identified as misconduct. Topics include: Introduction on Responsible Research and Innovation Research misconduct Authorship Plagiarism Peer reviews Conflicts of interest Mentor/mentee relationship Collaborative research Presenting the results Intellectual Property Information Privacy

Frriday, 11:00-13:00

Typed functional programming languages allow for the rapid development of robust programs. This course explores some of the more advanced language features of Haskell, a state­ of­ the­ art functional programming language, together with some of its theoretical background. The course aims to teach not only some of the more recent Haskell features, such GADTs or type families, but also the underlying theory. Besides the lectures, there are numerous supervised lab sessions to help you come to grips with the material covered in class. Advanced Functional Programming logo We expect students to have a basic familiarity with Haskell already. You should be able to write recursive functions over algebraic data types, such as lists and trees. There is a great deal of online material freely available that covers this material. From these basics, we aim to cover several more advanced topics, including monads, applicative functors, GADTs, (typed) lambda calculus, and generic programming. Each day we aim to cover a variety of topics in the lectures, mixing both practical programming advice and theoretical foundations. The supervised daily lab sessions offer students the opportunity to practice the material and discuss their problems with our Haskell experts.

9-18