Speaker: Arvind, Johnson Professor of Computer Science and Engineering at MIT.
Date: 27/06/2017 Time: 11:00
Venue: FIB building (B6), (Events room "Sala d'Actes Manuel Martí Recober"), Campus Nord, BarcelonaFriday 23 June 2017
Historically memory models for multiprocessors have not been designed deliberately but have just emerged. Practically every microarchitectural optimization, which is transparent in a single threaded setting, becomes programmatically visible in a multithreaded setting. This has created a cottage industry for masochists who try to classify and understand every nuance of permitted behaviors.
RISC-V offers us a unique opportunity to fix this historical wrong: specify a memory model first and make implementations conform to it. We will discuss the current proposals being debated for RISC-V memory model and point out the salient issues in this debate. These issues are atomic vs non-atomic memory systems, permitted instruction reorderings especially in the presence of dependencies, fences to control instruction reordering and ease of porting TSO programs to RISC-V. You will have a chance to express your opinions which I will report to the committee.
Further details: A Memory Model for RISC-V