This is a graduate course on the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems with an emphasis on a quantitative approach to cost/performance design tradeoffs. The course covers the fundamentals of classical and modern processor design: performance and cost issues, instruction sets, pipelining, caches, physical memory, virtual memory support, superscalar and out-of-order instruction execution.
Person in charge
Roger Espasa Sans (
Technical Competences of each Specialization
High performance computing
CEE4.1 - Capability to analyze, evaluate and design computers and to propose new techniques for improvement in its architecture.
Generic Technical Competences
CG5 - Capability to apply innovative solutions and make progress in the knowledge to exploit the new paradigms of computing, particularly in distributed environments.
CTR6 - Capacity for critical, logical and mathematical reasoning. Capability to solve problems in their area of study. Capacity for abstraction: the capability to create and use models that reflect real situations. Capability to design and implement simple experiments, and analyze and interpret their results. Capacity for analysis, synthesis and evaluation.
CB6 - Ability to apply the acquired knowledge and capacity for solving problems in new or unknown environments within broader (or multidisciplinary) contexts related to their area of study.
Basic understanding of the processor microarchitecture.
Assessment the performance of a processor.
Understanding of concurrency techniques transparent to the programmer used by processors to reduce the execution time.
Knowledge of a hardware description language and application in the design of digital systems.
1. Von-Neumann Architecture and performance
Von Neumann machine, performance metrics and technology outlook
2. Linearly pipelined processor
Datapath. Structural, Control and Data Hazards.
3. Techniques to increase the number of instructions executed per unit of time
Static code planification, shortcircuits.
4. Techniques to reduce the effective latency of memory
Caches. Store and Load management.
5. Multicicle Pipelined Processor and Software Optimizations
Multicicle pipeline. Datapath with multiple pipelines. Software transformations to increase the instruction level parallelism.
Branch Prediction and Exception Handling
Static and Dynamic Branch Prediction. Speculative Execution, Precise Exception handling.
Superscalar and out-of-order processors
Register Renaming. Out-of-Order handling.
Design Tools and Simulators
Learn the design and simulation tools. The student will cover the building blocks of the datapath of a microprocessor. Objectives:1234 Contents:
Course exams and tests Objectives:1234 Week:
The main concepts of processor architecture will be introduced in the lectures. In the interactive problem-solving classes the students will participate into applying the concepts learned into real world designs. Finally, the students will complete their learning experience with the lab sessions where they will put in practice the concepts learned in the lectures and applied in the problem-solving classes.
The course has two marks:
1) The final exam (F)
2) The microprocessor project (P) to be done in the Lab
The final mark will be computed as: 0,6 x P + 0,4 F.
The project requires at least a score of 5 points (out of 10), or the course will be failed.