The main objective of this course is that students acquire the fundamentals of the microarchitecture techniques used in high performance computers, considering the implications for energy and power. Another objective is the acquisition of architectural techniques used to efficiently support the implementation of operating systems.
The content of the course covers the application of pipelining techniques and parallelism in the processor design. In particular themes developed to enable evaluation of performance of a computing system to run applications and knowledge of the architecture to support an efficient implementation of operating systems. In addition to enable the use of hardware description languages and their use for the description of elements of a processor.
Person in charge
Jose M. Llaberia Griñó (
Miquel Moretó Planas (
Technical Competences of each Specialization
CTE1 - Capability to model, design, define the architecture, implement, manage, operate, administrate and maintain applications, networks, systems, services and computer contents.
CTE6 - Capability to design and evaluate operating systems and servers, and applications and systems based on distributed computing.
CTE7 - Capability to understand and to apply advanced knowledge of high performance computing and numerical or computational methods to engineering problems.
Generic Technical Competences
CG1 - Capability to plan, calculate and design products, processes and facilities in all areas of Computer Science.
CG3 - Capability to lead, plan and supervise multidisciplinary teams.
CG4 - Capacity for mathematical modeling, calculation and simulation in technology and engineering companies centers, particularly in research, development and innovation tasks in all areas related to Informatics Engineering.
CG6 - Capacity for general management, technical management and research projects management, development and innovation in companies and technology centers in the area of Computer Science.
CG8 - Capability to apply the acquired knowledge and to solve problems in new or unfamiliar environments inside broad and multidisciplinary contexts, being able to integrate this knowledge.
Appropiate attitude towards work
CTR5 - Capability to be motivated by professional achievement and to face new challenges, to have a broad vision of the possibilities of a career in the field of informatics engineering. Capability to be motivated by quality and continuous improvement, and to act strictly on professional development. Capability to adapt to technological or organizational changes. Capacity for working in absence of information and/or with time and/or resources constraints.
CB6 - Ability to apply the acquired knowledge and capacity for solving problems in new or unknown environments within broader (or multidisciplinary) contexts related to their area of study.
Learn to apply pipelining and parallelism techniques in the processor design.
Training to evaluate the performance of a computing system when running applications.
Training to exploit the capabilities of a computer system and stand or hide weaknesses.
Training to design and evaluate the architecture to support efficiently the implementation of operating systems.
Training for using a hardware description language and its application in the specification of processor elements.
Computer and performance metrics
Constituent elements of a computer, functioning, memory hierarchy, multithreaded, energy and performance metrics
Pipelining and parallelism
Using pipelining and parallelism techniques to increase productivity. Resources
Pipelining instruction execution
Data path of a linear pipelined processor and control. Concept of data hazard and control hazard. Adequacy of semantics
Software and hardware techniques to reduce the number of stall cycles in a pipelined processor
Parallel pipelines and superscalar processors
Interpretation of instructions for execution latency greater than the initiation latency. Using the technique of parallelism to interpret instructions
Exceptions and interrupts
Requirements in the data path and control for supporting interrupts and exceptions
Elements of a multiprocessor system. Private caches. Interconnection network. Concepts of memory consistency and cache coherence.
VHDL hardware description language
Learning a hardware description language
Hardware description language
Learning VHDL language to describe and simulate logic circuits. Description of basic components in the path of a data processor and its subsequent verification
Laboratory: Description and verification of a one-bit adder. Using the previous design to describe and verify a four-bit adder. Description and verification of a data path with register file and an adder
Autonomous learning: Learning basic VHDL constructs to describe combinational and sequential circuits. Learning circuit verification techniques. Preparation of the associated lab, answer questions and reflect on the answers
Study the data path of a serial processor. Identify the parts of the data path used for each type of instruction. Analysis and calculation of delay for each type of instruction and determining the cycle time of processor
Laboratory: Perform the actions and verifications indicated in the documentation
Autonomous learning: Study the documentation, answer questions and reflect on the answers
Evaluation of the consolidation of the concepts presented during the course by responding to questions and problems of reasoning about concepts presented Objectives:1234 Week:
15 (Outside class hours) Type:
Assessment goal for the first three issues Objectives:123 Week:
Assessment goal for the first three issues Objectives:123 Week:
Classes of theory in which concepts are developed and there is student participation.
Classes of problems where they apply the concepts developed in the lectures and the active agent is the student.
Laboratory classes where they apply the concepts developed in class theory in a concrete example of the processor. The active agent is the learner and collaboration between the elements of the group is a means to increase or establish knowledge.
The course develops contructiva. That is, some of the concepts learned in grade and in each issue of course increases the knowledge and ability to understand, analyze and reason about aspects of a processor. This training is also quantitative.
The powers have a weight proportional to the time spent in activities and they are evaluated indirectly based on midterm exam, final exam and laboratory.
The two midterm exams are performed simultaneously and are a single exam.
Midterm exam (P): Written test which evaluates the objectives for the first three issues.
Final exam (F): Written test which evaluates all objectives of the course.
Laboratory (L) is evaluated from the reports submitted in each of the practice sessions and, where appropriate, a personal interview.
The final note (NF) is calculated using the following expression:
NF = max (0.8 x F, (0.65 x F + 0.15 x P) ) + 0.2 x L
Combinational and sequential logic circuits. Operation of a computer: components, interconnections, exceptions and interrupts. Machine language: programming and data representation. Memory hierarchy: performance and mechanisms that support it. Operating Systems: address translation, interrupt and exception management
Where we are
B6 Building Campus Nord
C/Jordi Girona Salgado,1-3
08034 BARCELONA Spain
Tel: (+34) 93 401 70 00