VLSI

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Credits
6
Types
Specialization complementary (Computer Engineering)
Requirements
  • Prerequisite: AC
Department
AC
Web
http://docencia.ac.upc.edu/FIB/grau/VLSI
In the VLSI course, students will acquire the necessary knowledge to design and verify digital circuits. The syllabus provides a detailed and progressive approach to the manufacturing process of a modern processor (5% of the total course content). It particularly covers VLSI design at the CMOS transistor level (15%) and, in great depth, functional verification techniques, which constitute the main part of the course (80%). The objective is to equip students with a solid foundation in both CMOS design and verification, enabling them to tackle real-world projects. The course evaluation will be based on the completion of lab exercises and a project, which will be presented orally.

Teachers

Person in charge

  • Jesus Sanchez Navarro ( )

Weekly hours

Theory
2
Problems
0
Laboratory
2
Guided learning
0
Autonomous learning
6

Competences

Transversal Competences

Sustainability and social commitment

  • G2 [Avaluable] - To know and understand the complexity of the economic and social phenomena typical of the welfare society. To be capable of analyse and evaluate the social and environmental impact.
    • G2.3 - To take into account the social, economical and environmental dimensions, and the privacy right when applying solutions and carry out project which will be coherent with the human development and sustainability.

Technical Competences of each Specialization

Computer engineering specialization

  • CEC1 - To design and build digital systems, including computers, systems based on microprocessors and communications systems.
    • CEC1.2 - To design/configure an integrated circuit using the adequate software tools.
  • CEC3 - To develop and analyse hardware and software for embedded and/or very low consumption systems.
    • CEC3.2 - To develop specific processors and embedded systems; to develop and optimize the software of these systems. 

Objectives

  1. Understand the steps of VLSI circuit design. Get to know the tools available at each point.
    Related competences: CEC1.1, CEC1.2,
  2. Evaluate the VLSI circuits according to a set of figures of merit which include the economic and environmental evaluation
    Related competences: CEC1.2, G2.3,
  3. Get to know Hardware Description Languages. Be able to program simple structures in one of them
    Related competences: CEC1.2, G2.3,
  4. Understand hardware design specifications, develop a testbench, execute it, and be able to find errors in the design code.
    Related competences: CEC2.3, CEC3.2, CT6.2, CEC2.2,
  5. Present a verification plan in public and the results of its execution. Be able to conclude the verification of a hardware block.
    Related competences: CEC2.1, G4.3,

Contents

  1. Course description
    Introduction. Objectives. Phases in the development of a processor.
  2. Introduction to VLSI design at the CMOS transistor level
    Description of the stages and tools used in VLSI design, from system specification to implementation in an integrated circuit.
  3. The standard cell
    Designing with standard CMOS cells: principles, layout, and optimization for digital circuits.
  4. Introduction to pre-silicon verification
    What is pre-silicon verification? Relationship between design and verification. Types and objectives of verification. Simulation environment and tools.
  5. Verification planning and testbenches
    Basic structure and components of a testbench. Verification plan. Types of stimuli.
  6. SystemVerilog for verification
    Introduction to SystemVerilog for verification. Data types. Classes and inheritance. DPI.
  7. Assertions and functional coverage
    Types of assertions. SVA. Functional coverage.
  8. Introduction to UVM (Universal Verification Methodology)
    Why UVM? Components of a UVM testbench. Configuration and integration.
  9. Advanced UVM and practical applications
    Sequences. UVM factory. Best practices and design patterns.
  10. Processor verification
    Challenges at different pipeline stages. ISA verification. Cache coherence verification. Performance and power verification.
  11. Formal verification
    What is formal verification? Assertions as a formal basis. Limits and advantages of the method.
  12. Debug, coverage, and trends
    Debugging strategies. How to read and close functional coverage. Continuous verification.
  13. Introduction to post-silicon validation
    How errors are detected and resolved in real hardware. Tools and methodologies.

Activities

Activity Evaluation act


Foundations of VLSI design


Objectives: 1 2 3
Contents:
Theory
6.5h
Problems
0h
Laboratory
7h
Guided learning
0h
Autonomous learning
18h

Introduction to verification


Objectives: 3 4
Contents:
Theory
7.5h
Problems
0h
Laboratory
9h
Guided learning
0h
Autonomous learning
18h

Functional verification techniques


Objectives: 3 4
Contents:
Theory
7.5h
Problems
0h
Laboratory
10.5h
Guided learning
0h
Autonomous learning
18h

Specialized and formal verification


Objectives: 3 4
Contents:
Theory
4.5h
Problems
0h
Laboratory
3.5h
Guided learning
0h
Autonomous learning
12h

Debugging, trends, and validation


Objectives: 4
Contents:
Theory
4h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
12h

Verificacion project


Objectives: 3 4 5
Week: 14 (Outside class hours)
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
12h

Teaching methodology

The theory classes will cover the previously mentioned content, one topic per week, using slides (which will be shared with students). Student participation and engagement in class will be valued.

In the lab sessions, the concepts covered in theory will be applied, learning hands-on how to use EDA tools to design and/or verify hardware blocks commonly found in a modern microprocessor.

The course follows a constructive approach. That is, it builds on the concepts acquired in previous subjects, and with each topic, the student¿s knowledge and skills are progressively expanded.

Evaluation methodology

There are 2 components:

- Laboratory (L): lab grade, calculated based on each of the submissions.
- Presentation (P): individual oral presentation on a complete verification project.

The final grade will be calculated as: NF = 0.4 × L + 0.6 × P

The level of achievement of the generic competence is assessed indirectly through the lab grades and oral presentation. The corresponding mark is:

A if 8.5 <= NF; B if 7 <= NF < 8.5; C if 5 <= NF < 7; D if NF < 5

Bibliography

Basic:

Complementary:

Previous capacities

Those listed in IC, EC, PE and AC.