Computer Interfacing

Credits
6
Types
Compulsory
Requirements
  • Prerequisite: EC
  • Prerequisite: F
  • Prerequisite: IC
Department
ESAII
The course deeply deals with the Input / Output Computer system

Teachers

Person in charge

  • Antonio Camacho Santiago ( )

Others

  • Aleix Boixader Coma
  • Carlos Morata Núñez ( )
  • Enric X. Martin Rull ( )
  • Fabio Banchelli Gracia ( )
  • Josep Fernàndez Ruzafa ( )
  • Kilian Peiro Conde ( )
  • Manel Frigola Bourlon ( )
  • Manuel Vinagre Ruiz ( )
  • Toni Benedico Blanes ( )

Weekly hours

Theory
2
Problems
0
Laboratory
2
Guided learning
0.4
Autonomous learning
5.6

Competences

Technical Competences

Common technical competencies

  • CT2 - To use properly theories, procedures and tools in the professional development of the informatics engineering in all its fields (specification, design, implementation, deployment and products evaluation) demonstrating the comprehension of the adopted compromises in the design decisions.
    • CT2.3 - To design, develop, select and evaluate computer applications, systems and services and, at the same time, ensure its reliability, security and quality in function of ethical principles and the current legislation and normative.
    • CT2.5 - To design and evaluate person-computer interfaces which guarantee the accessibility and usability of computer systems, services and applications.
  • CT4 - To demonstrate knowledge and capacity to apply the basic algorithmic procedures of the computer science technologies to design solutions for problems, analysing the suitability and complexity of the algorithms.
    • CT4.1 - To identify the most adequate algorithmic solutions to solve medium difficulty problems.
  • CT5 - To analyse, design, build and maintain applications in a robust, secure and efficient way, choosing the most adequate paradigm and programming languages.
    • CT5.2 - To know, design and use efficiently the most adequate data types and data structures to solve a problem.
    • CT5.3 - To design, write, test, refine, document and maintain code in an high level programming language to solve programming problems applying algorithmic schemas and using data structures.
    • CT5.6 - To demonstrate knowledge and capacity to apply the fundamental principles and basic techniques of parallel, concurrent, distributed and real-time programming.
  • CT6 - To demonstrate knowledge and comprehension about the internal operation of a computer and about the operation of communications between computers.
    • CT6.2 - To demonstrate knowledge, comprehension and capacity to evaluate the structure and architecture of computers, and the basic components that compound them.
  • CT7 - To evaluate and select hardware and software production platforms for executing applications and computer services.
    • CT7.1 - To demonstrate knowledge about metrics of quality and be able to use them.
    • CT7.2 - To evaluate hardware/software systems in function of a determined criteria of quality.
    • CT7.3 - To determine the factors that affect negatively the security and reliability of a hardware/software system, and minimize its effects.
  • CT8 - To plan, conceive, deploy and manage computer projects, services and systems in every field, to lead the start-up, the continuous improvement and to value the economical and social impact.
    • CT8.1 - To identify current and emerging technologies and evaluate if they are applicable, to satisfy the users needs.
    • CT8.4 - To elaborate the list of technical conditions for a computers installation fulfilling all the current standards and normative.

Transversal Competences

Third language

  • G3 [Avaluable] - To know the English language in a correct oral and written level, and accordingly to the needs of the graduates in Informatics Engineering. Capacity to work in a multidisciplinary group and in a multi-language environment and to communicate, orally and in a written way, knowledge, procedures, results and ideas related to the technical informatics engineer profession.
    • G3.1 - To understand and use effectively handbooks, products specifications and other technical information written in English.

Objectives

  1. Explain the various functions and define the main parameters of an I/O interface.
    Related competences: CT6.2, CT2.5,
  2. Describe the block configuration for various input/output subsystems
    Related competences: CT6.2, CT2.5,
    Subcompetences:
    • Describe the block configuration for microcomputer input/output ports.
    • Describe the block configuration for microcomputer timers.
    • Describe the block configuration for microcomputer A/D converters.
    • Describe the block configuration for microcomputer interrupt controllers.
  3. Given the specifications for a particular microcomputer, program the various subsystems necessary to exchange data with the outside world and create and maintain programs that implement inputs and outputs using digital, analogue, pulse, parallel, serial, synchronous and asynchronous interfaces.
    Related competences: G3.1, CT6.2, CT2.5, CT4.1, CT5.2, CT5.3, CT5.6,
  4. Identify the components and signals in different block diagrams for microcomputer architecture and indicate their use. They should be able to identify data and instruction paths and determine the value of the different registers involved in each execution phase for a given instruction.
    Related competences: CT6.2,
  5. Given a diagram for a simple electronic circuit connected to a specific microcomputer pin, quantify the different technological parameters (intensities, voltages, resistance, noise, maximums, etc.), identify possible sources of error and size the different components.
    Related competences: CT7.1, CT7.2, CT7.3, CT6.2, CT2.5, CT2.3,
  6. Quantify the resolution of an I/O operation and calculate quantification and sampling errors.
    Related competences: CT7.1, CT7.2, CT2.5,
  7. Program multiplexed input and output operations for a given interconnection diagram for a device with a microcomputer and calculate sampling frequencies.
    Related competences: CT7.1, CT6.2, CT2.5, CT5.3, CT5.6,
  8. Describe how to handle an interrupt from request to end of service and calculate, given a program and microcomputer specifications, the service time for an interrupt, latency time and the order in which different requests are served.
    Related competences: G3.1, CT7.1, CT6.2,
  9. Program, given the specifications for a microcomputer and for all possible interrupt sources, service routines for the different interrupts while ensuring guaranteed time of service, program context recovery and restoration and identify critical regions.
    Related competences: G3.1, CT6.2, CT4.1, CT5.3, CT5.6, CT2.3,
  10. Explain the characteristics of different types of storage, choose suitable storage for a specific context and measure width and capacity for different memories and the width of access buses.
    Related competences: CT8.1, CT7.1, CT7.2, CT7.3, CT6.2, CT2.3,
  11. Size the number of bits and work frequency for a timer and generate a signal of a specific frequency and duty cycle and lags for the desired duration. Students should also be able to accurately measure the period or frequency of an input signal, the instant when a pulse event occurs and the interval between two events.
    Related competences: CT7.1, CT6.2, CT2.5,
  12. Define and explain serial communication parameters, features and possible errors. Explain the differences in serial communication standards (UART, SPI, I2C, 1-Wire, CAN, etc.).
    Related competences: CT8.1, CT6.2, CT8.4, CT2.5,
  13. Describe the main features and functions of the USB bus and hub.
    Related competences: CT8.1, CT6.2, CT8.4, CT2.5,
  14. Describe the types and formats of USB packets, the packet transaction protocol in the presence and absence of errors, different types of endpoints and their performance in terms of speed, bus use, bandwidth warranty and error handling.
    Related competences: CT7.1, CT7.3, CT6.2, CT2.5,
  15. Locate a peripheral in the hierarchy of buses in the computer architecture.
    Related competences: CT8.1, CT6.2, CT2.5,
  16. Calculate the minimum expected transfer time between a memory and a device or between devices. They should also be able to draw the data path for different types of transfers and locate bottlenecks in multiple transfers between devices.
    Related competences: CT7.1, CT7.2, CT7.3, CT6.2, CT2.3,
  17. Quantify bus throughput at different levels (internal bus, local bus, system bus, expansion bus, peripheral buses) and explain the features of a bridge between buses.
    Related competences: CT8.1, CT7.1, CT7.2, CT7.3, CT6.2,
  18. Describe the basic I/O interconnection device configuration with DMA transfer and link DMA operational modes with the operations of different buses in the computer hierarchical structure. They should also be able to compare transfer time in a bus with and without DMA.
    Related competences: CT7.1, CT7.2, CT6.2, CT2.5,
  19. Correctly interpret technical descriptions, block diagrams, electronic diagrams and schedules in reference manuals and prepare the documentation necessary to transfer knowledge and ideas (block diagrams, electronic diagram, flowcharts, state diagrams, component lists, etc.).
    Related competences: G3.1, CT5.3,
  20. Understand hardware in relation to the installation, maintenance, identification, manipulation and interconnection of systems and apply device connection techniques to microcomputer pins.
    Related competences: CT7.3, CT6.2, CT2.5, CT2.3,
  21. Resolve the hardware/software trade-off in the implementation of a particular I/O function and program with limited resources.
    Related competences: CT7.2, CT7.3, CT2.5, CT4.1, CT5.2, CT5.3, CT5.6,
  22. Solve the time and stability requirements for an I/O system.
    Related competences: CT7.2, CT7.3, CT2.5, CT5.6, CT2.3,
  23. Use the main circuit analysis tools (simulator, emulator, logic analyser, debuggers and ROM monitors) and detect and understand their limitations.
    Related competences: CT8.1, G3.1, CT7.1, CT7.2, CT7.3, CT5.3,

Contents

  1. Introduction
    Definition of interface. Types of interfaces. Interface levels. Typical interface mechanisms. Example interfaces.
  2. Microcomputer architecture
    Microcomputers. Families. Block diagram of a specific microcontroller with its features and functions. Instruction cycle stages. Pipe-line execution of instructions. The arithmetic logic unit (ALU). Data paths. Special registers. Memory. Instruction format. Addressing modes. Assembly language structure (instructions, guidelines, examples of use).
  3. Input/output ports
    I/0 port structure. * status and control data registers * bidirectional pin operation * bus connection. Three-state output. Z state. Technological considerations. Connections to external loads. Input device connections. Signal multiplexing.
  4. Interrupts
    Synchronisation mechanisms: polling, interrupts. Parameters: latency, priority, throughput, service time. Interrupt sources. Hierarchy. Masking. Priorities. Daisy chain. Interrupt sequences. Interrupt vectors. Service routines. Programming guide. Saving and restoring context. Exceptions and interrupts.
  5. Impulse inputs and outputs
    Programmable time controller diagram. Main time controller working modes. Time controllers to count asynchronous events. Generating output impulses using IT. Generating modulated signals in pulse width modulation (PWM) using IT.
  6. Analogue Interfaces
    Timing and frequency aspects of analogue signals. Nyquist-Shannon sampling theorem. Analogue-digital converters. Digital-analogue converters. Example application.
  7. Serial communication interfaces
    Types and characteristics of communication interfaces. Synchronous serial interface (SSI). A real example (RS232). Synchronous serial interface (SSI). A real example (SPI). USB for peripheral devices.
  8. Buses and DMA
    Width, frequency and transfer concepts. Bus width, bus frequency, transfer rate. Bus hierarchies. Bus rearrangement and the PCIe bus. Bus partitioning and addressing concepts. Bus controllers. The concept of bridge. Modifying address, width and frequency spaces, buffering. Bus peripheral controllers. Bus transfer acceleration. DMA. DMA levels. DMA operation. Classical functioning modes. Calculating transfers with DMA.

Activities

Activity Evaluation act


Development of item 1 of the course


Objectives: 1 2 19
Contents:
Theory
2h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Development of item 2 of the course


Objectives: 1 2 3 4 6 10 16 19
Contents:
Theory
4h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
6h

Development of item 3 of the course


Objectives: 1 2 3 4 5 7 19 20 22
Contents:
Theory
4h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
6h

Development of item 4 of the course


Objectives: 4 8 9 22
Contents:
Theory
2h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
3h

Development of item 5 of the course


Objectives: 1 2 3 4 6 11 19 22
Contents:
Theory
2h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
3h

Development of item 6 of the course


Objectives: 1 2 3 4 6 7 19
Contents:
Theory
2h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
3h

Development of item 7 of the subject


Objectives: 1 2 3 4 12 13 14 19 20
Contents:
Theory
6h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
9h

Development of the subject item 8


Objectives: 1 2 15 16 17 18 19 21 22
Contents:
Theory
4h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
6h

Practice 1


Objectives: 19 20 23
Contents:
Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Practice 2


Objectives: 3 4 5 19 20 21 23
Contents:
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
3h

Practice 3


Objectives: 3 4 19 20 21 22 23
Contents:
Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Practice 4


Objectives: 3 4 19 20 21 22 23
Contents:
Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Practice 5


Objectives: 4 5 7 19 20 21 22 23 3
Contents:
Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
2h
Guided learning
0h
Autonomous learning
3h

Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

First partial test


Objectives: 1 2 3 4 5 6 7 10 19 20 21
Week: 6 (Outside class hours)
Type: theory exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
1h
Autonomous learning
8h

Second partial test


Objectives: 2 3 4 6 7 8 9 11 19 20 21 22
Week: 12 (Outside class hours)
Type: theory exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
1h
Autonomous learning
8h

Third partial test


Objectives: 2 3 4 12 13 14 15 16 17 18 19 20 21 22
Week: 14 (Outside class hours)
Type: theory exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
1h
Autonomous learning
8h

Practical implementation of a microcomputer


Objectives: 3 4 5 19 20 21 23
Week: 2
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice I/ O Ports


Objectives: 3 4 5 19 20 21 23
Week: 3
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice the 7 segment


Objectives: 3 4 19 20 21 23
Week: 4
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Keyboard Practice


Objectives: 3 4 5 6 7 19 20 21 22 23
Week: 5
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice interruptions


Objectives: 3 4 8 9 19 20 21 22 23
Week: 6
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Timers Practice


Objectives: 3 4 6 9 11 19 21 22 23
Week: 7
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice counters


Objectives: 3 5 6 9 11 19 20 21 22 23
Week: 8
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice converter A / D


Objectives: 3 4 5 6 7 9 19 20 21 22 23
Week: 9
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice serial com


Objectives: 3 4 9 12 19 20 21 22 23
Week: 10
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice mouse


Objectives: 3 4 9 13 14 19 20 21 22 23
Week: 11
Type: final exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice USB


Objectives: 3 4 9 13 14 19 20 21 22 23
Week: 12
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice 1Wire


Objectives: 3 4 5 9 12 19 20 21 22 23
Week: 13
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Practice touchscreen and GLCD


Objectives: 3 4 5 6 7 9 19 20 21 22 23
Week: 14
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Final Exam

Only those students who have requested within the deadline
Objectives: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Week: 15
Type: final exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Examination practice


Objectives: 3 4 5 6 7 8 9 11 19 20 21 22 23
Week: 15 (Outside class hours)
Type: lab exam
Theory
0h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
0h

Teaching methodology

No distinction is drawn between theory and problem-solving classes. Theory is reinforced with examples showing alternatives and solutions to interface problems.
Self-assessment exercises are proposed in the various topics so that students can assess their own progress. Students may consult the lecturer as necessary.
The practical sessions will take place in situ in the FIB teaching laboratory. An essential requirement for each practical is to have performed a pre-set task (to be specified).

Evaluation methodology

* During the course will take a minimum of 3 written tests corresponding to different parts of the course. Be made individually. Obtained a note (NT) from the average of the assessments.

* The grade laboratory NL obtained from the average of the individual assessments of practices . There will be between 10 and 14 evaluable practices during the year. The written tests will contain lab questions that will help to individualise the marks.

Students repeat the practices that are approved to be validated practices NL = 5.

* The final grade for the course comes from :

NF = 0.65NT +0.35 NL

* It is a necessary condition for passing the subject and presented properly perform laboratory practices.

Bibliography

Basic:

Previous capacities

Students are expected to be able to:
Program in a high-level language (preferably C).
Program in an assembly language.
Understand the functioning of different electronic components: R, L, C, diodes, MOS transistors.
Understand DC electronic circuits and voltage, current and consumption calculations.
Represent numbers in the binary and hexadecimal bases and performing arithmetic and logical operations on them.
Understand the functioning of the different logic gates and combinational and sequential blocks.
Understand how to analyse and synthesise logic circuits.
Understand processor structure and operation.
Understand the architecture and operation of a simple computer.
Understand computer memory operations and hierarchy.
Understand documents written in English.

Addendum

Contents

NO HI HA CANVIS RESPECTE LA INFORMACIÓ PUBLICADA A LA GUIA DOCENT

Teaching methodology

NO HI HA CANVIS RESPECTE LA INFORMACIÓ PUBLICADA A LA GUIA DOCENT

Evaluation methodology

Aquest quadrimestre hi hauran dos parcials (P1 i P2). La nota de teoria es calcularà en base a aquest dos parcials NT = (P1 + P2)/2

Contingency plan

En cas d'emergència sanitària pel COVID-19, les classes es realitzaran on-line i es mantindran síncrones via gmeet. El laboratori es realitzaran de forma síncrona amb gmeet i els simuladors Proteus disponibles via escriptori remot.