Processor Verification

• Weekly hours
• Objectives
• Contents
• Activities
• Teaching methodology
• Evaluation methodology
• Bibliography
• Previous capacities

Teachers

Person in charge

• Jesus Sanchez Navarro ( )

Weekly hours

Objectives

1. To understand and implement a verification plan and a testbench, and execute it.
   Related competences: CG4, CEE4.1, CB7, CTR3,
2. To be able to provide and defend the verification plan and its execution phases.
   Related competences: CB8, CTR3, CTR5,
3. To use the EDA tools required to accomplish the project.
   Related competences: CB7, CTR5,

Contents

1. Introduction to pre-silicon verification
   Why verification is critical in modern design. Overview of the verification flow. The role of
   verification in microprocessor design.
2. Verification planning and testbenches
   Verification plan and coverage goals. Testbench architecture. Monitors, checkers, and scoreboards.
3. SystemVerilog for verification (SVV)
   SystemVerilog basics for testbench design. Interfaces and clocking blocks. Randomization and constraints. Classes, inheritance, polymorphism. Transactions (TLM).
4. Directed and randomized tests
   Directed test methodologies. Randomized test generation. Test coverage analysis. Debugging strategies. Stimulus variation. Predictability vs. randomness. Constraints in test generation.
5. Assertions and functional coverage
   Immediate vs. concurrent assertions. SVA (SystemVerilog Assertions) syntax and
   examples. Functional coverage vs. code coverage. Coverage-driven verification.
6. Introduction to UVM (Universal Verification Methodology)
   UVM goals and structure. UVM components. Factory, configuration, and objection mechanisms.
7. UVM testbenches and sequencing
   UVM test phases and flow. Sequences and sequence items. Building reusable tests. Debugging and simulation output.
8. Processor-specific verification challenges
   Verifying CPU pipelines and control logic. Instruction-level and architectural verification. Handling interrupts, exceptions, and hazards. ISA compliance testing.
9. Formal verification techniques
   Model checking and theorem proving overview. Equivalence checking. Bounded model
   checking. Use cases and limitations in microprocessor design.
10. Performance and power verification
    Power-aware simulation concepts. Functional vs. low-power states. Performance modeling.
11. Debug strategies and coverage closure
    Interpreting functional/code coverage reports. Optimizing tests for coverage. Debugging techniques and waveform analysis.
12. Trends and real-case studies
    Latest trends in verification (RISC-V, ML-driven verification, formal tools). Review of real CPU verification case studies.
13. Introduction to post-silicon validation
    How errors are detected and fixed in real hardware. Tools and methodologies.

Activities

Activity Evaluation act

Teaching methodology

Evaluation methodology

Bibliography

Basic:

• SystemVerilog for Verification: A Guide to Learning the Testbench Language Features - Spear, Chris ; Tumbush, Greg, Springer Nature, 3rd ed. 2012. ISBN: 9781461407157
  https://discovery.upc.edu/discovery/fulldisplay?docid=cdi_springer_books_10_1007_9 78_1_4614_0715_7&context=PC&vid=34CSUC_UPC:VU1&lang=ca
• The UVM primer : an introduction to the Universal Verification Methodology - Salemi, Ray, Boston Light Press, 2013. ISBN: 9780974164939
  https://discovery.upc.edu/discovery/fulldisplay?docid=alma991005224879506711&con text=L&vid=34CSUC_UPC:VU1&lang=ca

Previous capacities