Computer Architecture II

Credits
6
Types
Specialization compulsory (Computer Engineering)
Requirements
Department
AC
AC-2 describes the internal implementation of the processor at the architecture level. It introduces the segmentation-based implementation and then introduces performance enhancements such as short-circuits and instruction reordering/scheduling mechanisms.

Teachers

Person in charge

Others

Weekly hours

Theory
2
Problems
1
Laboratory
1
Guided learning
0
Autonomous learning
6

Competences

Technical Competences

Common technical competencies

  • CT6 - To demonstrate knowledge and comprehension about the internal operation of a computer and about the operation of communications between computers.
    • CT6.2 - To demonstrate knowledge, comprehension and capacity to evaluate the structure and architecture of computers, and the basic components that compound them.
  • CT7 - To evaluate and select hardware and software production platforms for executing applications and computer services.
    • CT7.1 - To demonstrate knowledge about metrics of quality and be able to use them.

    • Transversal Competences

    Reasoning

  • G9 [Avaluable] - Capacity of critical, logical and mathematical reasoning. Capacity to solve problems in her study area. Abstraction capacity: capacity to create and use models that reflect real situations. Capacity to design and perform simple experiments and analyse and interpret its results. Analysis, synthesis and evaluation capacity.
    • G9.3 - Critical capacity, evaluation capacity.

    • Technical Competences of each Specialization

    Computer engineering specialization

  • CEC1 - To design and build digital systems, including computers, systems based on microprocessors and communications systems.
    • CEC1.1 - To design a system based on microprocessor/microcontroller.
    • CEC1.2 - To design/configure an integrated circuit using the adequate software tools.
  • CEC2 - To analyse and evaluate computer architectures including parallel and distributed platforms, and develop and optimize software for these platforms.
    • CEC2.1 - To analyse, evaluate, select and configure hardware platforms for the development and execution of computer applications and services.
  • CEC3 - To develop and analyse hardware and software for embedded and/or very low consumption systems.
    • CEC3.2 - To develop specific processors and embedded systems; to develop and optimize the software of these systems. 

    • Objectives

    1. Understanding concurrency techniques transparent to the programmer of machine language used by processors to reduce the execution time.
      Related competences: CT6.2,
    2. Understand some of the technological constraints in the implementation of a processor.
      Related competences: CT6.2,
    3. Knowledge of a hardware description language (VHDL) and application in the design of digital systems.
      Related competences: CEC3.2, CEC1.1, CEC1.2, CT6.2,
    4. Training to assess the performance of a processor.
      Related competences: G9.3, CEC2.1, CT7.1,
    5. Basic understanding of the processor microarchitecture .
      Related competences: CEC3.2, CT6.2,

    Contents

    1. Von-Neumann architecture and performance.
      Von-Neumann machine. Performance metrics. Manufacturing Technology.
    2. Techniques to increase the number of operations per unit time.
      Pipelining and replication. Interpretation of instructions. Structural hazards.
    3. Linear pipeline processor.
      Datapath. Dependencies between instructions. Data hazards. Control hazards.
    4. Techniques to reduce and tolerate the pipeline effective latency.
      Static instruction scheduling. Data bypasses. Fixed branch prediction.
    5. Pipeline with multicycle operations.
      Multicycle operations. Datapath with parallel pipelines. Code transformations to exploit instruction-level parallelism .

    Activities

    Activity Evaluation act


    Design tools and simulation

    Learning tools for specification and simulation of logic circuits. Review of the operation and basic characteristics of the components of a single-cycle datapath.
    Objectives: 3
    Contents:
    Theory
    0h
    Problems
    0h
    Laboratory
    6h
    Guided learning
    0h
    Autonomous learning
    9h

    Von-Neumann machine and performance

    Development of item 1 of the course
    Objectives: 4 2
    Contents:
    Theory
    4h
    Problems
    2h
    Laboratory
    0h
    Guided learning
    0h
    Autonomous learning
    10h

    Techniques to increase the number of operations per unit time

    Development of item 2 of the course
    Objectives: 5 4 1
    Contents:
    Theory
    5h
    Problems
    3h
    Laboratory
    0h
    Guided learning
    0h
    Autonomous learning
    10h

    Linear pipeline processor

    Development of item 3 of the course
    Objectives: 5 4 1
    Contents:
    Theory
    7h
    Problems
    3h
    Laboratory
    4h
    Guided learning
    0h
    Autonomous learning
    14h

    Partial Test


    Objectives: 5 4 1 2
    Week: 8
    Theory
    0h
    Problems
    0h
    Laboratory
    0h
    Guided learning
    0h
    Autonomous learning
    0h

    Techniques to reduce and tolerate pipeline effective latency

    Development of item 4 of the course
    Objectives: 5 4 1
    Theory
    4h
    Problems
    4h
    Laboratory
    5h
    Guided learning
    0h
    Autonomous learning
    14h

    Processor with multicycle operations

    Development of item 5 of the course
    Objectives: 5 4 1
    Contents:
    Theory
    5h
    Problems
    3h
    Laboratory
    0h
    Guided learning
    0h
    Autonomous learning
    11h

    Consolidation

    Consolidation of concepts developed during the course
    Objectives: 5 4 1 2 3
    Contents:
    Theory
    0h
    Problems
    0h
    Laboratory
    0h
    Guided learning
    0h
    Autonomous learning
    6h

    Final Exam


    Objectives: 5 4 1 2 3
    Week: 15 (Outside class hours)
    Theory
    0h
    Problems
    0h
    Laboratory
    0h
    Guided learning
    0h
    Autonomous learning
    0h

    Teaching methodology

    In the theory classes expose the concepts of the course with student participation.
    The exercice classes the students apply the theoretical concepts in solving exercises.
    In laboratory classes students work in small groups and apply the concepts on a simple pipelined processor.

    Evaluation methodology

    There are three elements:

    Final (F): final written exam covering all the objectives of the course. Partial (P): written test on the first three topics.
    Lab (L) from the reports made in each of the sessions and, where appropriate, a personal interview.

    NF = 0.2 x L + max[0.8 x F, (0.65 x F + 0.15 x P)]

    Bibliography

    Basic

    Complementary

    Previous capacities

    Combinational and sequential logic circuits. Operation of a computer: components and interconnections. Machine language: programming and data representation. Hierarchy of memory: performance and mechanisms that support it. Elementary statistical calculus.