Person in charge: | (-) |
Others: | (-) |
Credits | Dept. |
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7.5 (6.0 ECTS) | AC |
Person in charge: | (-) |
Others: | (-) |
The aim of this subject is to allow students to be familiar with VLSI technologies and their potential, limitations and areas of application. Students learn how the basic structures of microprocessors are organized at the transistor level and the implications of the technology in the design. Also, they learn how to use circuit design tools and how to design VLSI circuits of medium complexity.
Estimated time (hours):
T | P | L | Alt | Ext. L | Stu | A. time |
Theory | Problems | Laboratory | Other activities | External Laboratory | Study | Additional time |
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T | P | L | Alt | Ext. L | Stu | A. time | Total | ||
---|---|---|---|---|---|---|---|---|---|---|
8,0 | 2,0 | 2,0 | 0 | 0 | 10,0 | 0 | 22,0 | |||
Basic concepts - The characteristics of CMOS technology will be described in this theme. The basic workings of MOS transistors will be described at both the logic and physical levels. The rules for designing circuits and the way they are manufactured will be discussed. The way in which transistors are combined in the design of simple and complex CMOS gates will also be explained. The evaluation of the basic parameters of transistors will also be covered.
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T | P | L | Alt | Ext. L | Stu | A. time | Total | ||
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10,0 | 4,0 | 4,0 | 0 | 0 | 14,0 | 0 | 32,0 | |||
How to calculate the design parameters: area, delay, power consumption. The content will also explain how to characterise a circuit in modular form.
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T | P | L | Alt | Ext. L | Stu | A. time | Total | ||
---|---|---|---|---|---|---|---|---|---|---|
10,0 | 4,0 | 4,0 | 0 | 0 | 14,0 | 8,0 | 40,0 | |||
The design of super-buffers, and other logic families will be described: pass gates, pseudo nMOS.
The workings of dynamic logic will be explained, together with some of its variations. Clock generation and distribution will also be covered.
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T | P | L | Alt | Ext. L | Stu | A. time | Total | ||
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15,0 | 5,0 | 4,0 | 0 | 8,0 | 20,0 | 0 | 52,0 | |||
The elements comprising microprocessors at the transistor level will be described: latches, registers, memories, ALUS, register banks.
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Total per kind | T | P | L | Alt | Ext. L | Stu | A. time | Total |
45,0 | 15,0 | 14,0 | 0 | 8,0 | 60,0 | 8,0 | 150,0 | |
Avaluation additional hours | 4,5 | |||||||
Total work hours for student | 154,5 |
The theory classes will take the form of lectures and problems.
Students will solve the exercises set by the teacher. The various solutions will be discussed at the end of the class.
In the lab classes, students will solve the exercises previously set by the teacher. The problems will be previously made available. At the end of the class, students have to submit a brief report on their findings. The final practical session involves great effort on students" part and consequently, a longer report will be required.
The assessment is based on the following grades:
P1, P2: part tests
EF: Final Exam
L: Lab grade
Students obtaining the following grades: P1>=3.5 i P2>=3.5 may receive their final grade without having to sit the Final Exam, providing (P1+P2)/2 >= 5.0 (P1 and P2 are graded out of 10):
NF = 0.4 * (P1+P2) + 0.2 * L
The remaining students must sit the Final Exam and their final grade will be calculated as follows:
NF = 0.8 * EF + 0.2 *L
In any event, students opting for the Final Exam may increase their final grade, which will be the highest yielded by either of the two formulae above.
There is no additional restriction on the Final Exam and Lab grades.
Attendance at the P1 and P2 part exams is completely voluntary.
Previous knowledge of computer architecture will be useful. Specifically, students should have passed the Computer Architecture (AC) course.