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Credits Dept.
7.5 (6.0 ECTS) BSC


Person in charge:  (-)

General goals

The goal of this course is to present the design of a supercomputer system, from the architecture of the individual core of a multicore chip in a shared-memory node, to the distributed memory system and the high bandwidth interconnection network. This knowledge will allow application developers to exploit the characteristics of the underlying system in order to write more efficient code.

Specific goals


  1. To understand the basic concepts about microprocessor architecture.
  2. To understand the basic concepts about shared and distributed multiprocessor systems.


  1. To be able to exploit the characteristics of a target architecture to improve application performance.
  2. To identify potential bottlenecks in application performance.
  3. To identify the desirable system properties for a target application.


  1. Be able to work individually or in group to discover the architectural issues that affect the performance of a specific application.


Estimated time (hours):

T P L Alt Ext. L Stu A. time
Theory Problems Laboratory Other activities External Laboratory Study Additional time

1. Processor architecture.
T      P      L      Alt    Ext. L Stu    A. time Total 
8,0 0 0 0,5 0 8,0 0 16,5
1.1 Instruction set architecture: RISC, CISC, SIMD extensions.
1.2 Instruction pipelining, superscalar execution, out-of-order execution.
1.3 Cache memory hierarchy.

2. Multiprocessor architecture.
T      P      L      Alt    Ext. L Stu    A. time Total 
10,0 0 0 0,5 0 8,0 0 18,5
2.1 Multithreaded processors.
2.2 Shared memory multiprocessors.
- Memory coherence.
- Memory consistency.
2.3 Distributed memory multiprocessors.
- Distributed shared memory.

3. Interconnection networks.
T      P      L      Alt    Ext. L Stu    A. time Total 
6,0 0 0 0 0 6,0 0 12,0

4. Performance analysis tools.
T      P      L      Alt    Ext. L Stu    A. time Total 
8,0 0 6,0 0 0 4,0 0 18,0

5. Architecture conscious programming.
T      P      L      Alt    Ext. L Stu    A. time Total 
8,0 0 12,0 0 0 4,0 0 24,0
5.1 Improving single thread performance.
5.2 Improving multithreaded performance.
5.3 Improving multiprocessor performance.

Total per kind T      P      L      Alt    Ext. L Stu    A. time Total 
40,0 0 18,0 1,0 0 30,0 0 89,0
Avaluation additional hours 0
Total work hours for student 89,0

Docent Methodolgy

Theory classes building up concepts in a structured fashion and setting out the commitment required for their practical application. The classes will give a perspective of the future trends. Laboratory classes focusing on co-operative work in order to consolidate concepts, skills and competencies.

Evaluation Methodgy

Analysis of a set of selected architecture papers through a written report and an oral exposition. Optimization of a set of example applications for a candidate system architecture.

Basic Bibliography

  • J.P. Shen and M.H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, McGraw-Hill , 2005, First Edition.
  • J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishing Co, .
  • Duato, J., Yalamanchili, S., and Ni, L., Interconnection Networks: an Engineering Approach, 1st. IEEE Computer Society Press, 1997.

Complementary Bibliography

  • Proceedings of top computer architecture conferences: ISCA, MICRO, HPCA, ICS, Supercomputing, PACT, IPDPS, ICCD, ..., , .

Web links

(no available informacion)

Previous capacities

-  Undergraduate courses in structured programming.
-  Knowledge of C.
-  Notions of MPI, OpenMP, Pthreads.
-  Notions of computer architecture.


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