Processor Architecture

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Credits
6
Types
Specialization compulsory (High Performance Computing)
Requirements
This subject has not requirements, but it has got previous capacities
Department
AC
Web
none
Mail
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This is a graduate course on the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems with an emphasis on a quantitative approach to cost/performance design tradeoffs. The course covers the fundamentals of classical and modern processor design: performance and cost issues, instruction sets, pipelining, caches, physical memory, virtual memory support, superscalar and out-of-order instruction execution.

Teachers

Person in charge

  • Roger Espasa Sans ( )

Weekly hours

Theory
2
Problems
1
Laboratory
1
Guided learning
0
Autonomous learning
5.33

Competences

Technical Competences of each Specialization

High performance computing

  • CEE4.1 - Capability to analyze, evaluate and design computers and to propose new techniques for improvement in its architecture.

Generic Technical Competences

Generic

  • CG5 - Capability to apply innovative solutions and make progress in the knowledge to exploit the new paradigms of computing, particularly in distributed environments.

Transversal Competences

Reasoning

  • CTR6 - Capacity for critical, logical and mathematical reasoning. Capability to solve problems in their area of study. Capacity for abstraction: the capability to create and use models that reflect real situations. Capability to design and implement simple experiments, and analyze and interpret their results. Capacity for analysis, synthesis and evaluation.

Basic

  • CB6 - Ability to apply the acquired knowledge and capacity for solving problems in new or unknown environments within broader (or multidisciplinary) contexts related to their area of study.

Objectives

  1. Basic understanding of the processor microarchitecture.
    Related competences: CEE4.1,
  2. Assessment the performance of a processor.
    Related competences: CTR6, CEE4.1,
  3. Understanding of concurrency techniques transparent to the programmer used by processors to reduce the execution time.
    Related competences: CEE4.1, CG5,
  4. Knowledge of a hardware description language and application in the design of digital systems.
    Related competences: CB6, CEE4.1,

Contents

  1. 1. Von-Neumann Architecture and performance
    Von Neumann machine, performance metrics and technology outlook
  2. 2. Linearly pipelined processor
    Datapath. Structural, Control and Data Hazards.
  3. 3. Techniques to increase the number of instructions executed per unit of time
    Static code planification, shortcircuits.
  4. 4. Techniques to reduce the effective latency of memory
    Caches. Store and Load management.
  5. 5. Multicicle Pipelined Processor and Software Optimizations
    Multicicle pipeline. Datapath with multiple pipelines. Software transformations to increase the instruction level parallelism.
  6. Branch Prediction and Exception Handling
    Static and Dynamic Branch Prediction. Speculative Execution, Precise Exception handling.
  7. Superscalar and out-of-order processors
    Register Renaming. Out-of-Order handling.

Activities

Activity Evaluation act


Design Tools and Simulators

Learn the design and simulation tools. The student will cover the building blocks of the datapath of a microprocessor.
Objectives: 1 2 3 4
Contents:
Theory
0h
Problems
0h
Laboratory
8h
Guided learning
0h
Autonomous learning
16h

Basic architecture and performance metrics of the datapath of a microprocessor

Study the concepts associated to this chapter and solve the problems sets.
Objectives: 1 2
Contents:
Theory
4h
Problems
2h
Laboratory
4h
Guided learning
0h
Autonomous learning
20h

Techniques to speed-up the execution of the instructions

Learn the concepts explained in the theory sessions and solve the problem sets.
Objectives: 2 3
Contents:
Theory
6h
Problems
6h
Laboratory
6h
Guided learning
0h
Autonomous learning
20h

Multicycle, Superscalar and Out-of-Order Processors.

Learn the concepts explained in the theory sessions and solve the problem sets.
Objectives: 2 3
Contents:
Theory
8h
Problems
8h
Laboratory
0h
Guided learning
0h
Autonomous learning
20h

Exams/Tests (apart from the lab sessions)

Course exams and tests
Objectives: 1 2 3 4
Week: 15
Type: theory exam
Theory
2h
Problems
0h
Laboratory
0h
Guided learning
0h
Autonomous learning
20h

Teaching methodology

The main concepts of processor architecture will be introduced in the lectures. In the interactive problem-solving classes the students will participate into applying the concepts learned into real world designs. Finally, the students will complete their learning experience with the lab sessions where they will put in practice the concepts learned in the lectures and applied in the problem-solving classes.

Evaluation methodology

The course has two marks:
1) The final exam (F)
2) The microprocessor project (P) to be done in the Lab

The final mark will be computed as: 0,6 x P + 0,4 F.
The project requires at least a score of 5 points (out of 10), or the course will be failed.

Bibliography

Basic:

Complementary:

Previous capacities

Understanding of Digital System Design