ABSTRACT
Researchers at the Institute for Computing Technology within the Chinese Academy of Sciences have embarked on a very ambitious project: to redesign data centers to improve performance and energy efficiency at all levels, from creating more flexible and scalable topologies to streamlining network protocols and improving server architectures. For the past year, I have been working with ICT colleagues and students on workload characterization, system log analysis, network QoS, architectures to support flexible resource sharing, and memory system design. And unlike most academic research projects, much of the ICT work is based on real hardware designs and FPGA and/or ASIC prototypes. In this talk, I will present recent memory system designs and results, including an approach to reducing DRAM refresh power/performance penalties and an approach to building extendable DDRx DRAM memory subsystems. The ideas behind these designs are satisfyingly intuitive -- their true impact lies in the innovations that they themselves enable.

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