ABSTRACT

Error Correcting COdes (ECC) are commonly used to protect microprocessor cache against transient errors. Until now, the correction capabilities of ECC used for cache was remained constant, or has been slighly increased to take into account the increased likelihood of transient fault due to the technology shriking. But, the need of more energy efficient caches, require to lower power voltage, thus strongly decreasing the reliability of memories. It be considered that recently proposed aggressive power saving techniques push the memory error rate up to 5%!

This require a deep rethinking of the current available ECC codes for caches and open a lot of research opportunities. This talk will give an introduction to the current challenges of the design of ECC for caches and will present some recently proposed schemes to improve their efficiency. First I will describe the use of Ortoghonal Latin Square (OLS) codes for caches, and how to increase the code rate using extend OLS codes. After the use of Error Code Tagging is presented and its applications to different cache structures is described. Finally, an approach to trade-off the cache performances in terms of power consumption w.r.t. processing power that is based on changing the codeword used to protect the cache is presented.

BIOGRAPHY

Dr. Salvatore Pontarelli received the Master Degree in Electronic Engineering at University of Bologna in 2000. In 2003 he received the PhD Degree in Microelectronics and Telecommunications from the University of Rome Tor Vergata. Currently, he is with the Department of Electronic Engineering at the same university.

In the past Dr. Pontarelli has worked with the National Research Council (CNR), the Italian Space Agency (ASI), the National Inter-University Consortium for Telecommunications (CNIT) and has been consultant for various Italian and European companies for projects related to digital design and to fault tolerance in digital systems.

His research activities are mainly focused on : - Development of highly reliable systems for space applications, - Error detection and correction codes, with emphasis both on correction capability evaluations and on design of encoders and decoders, - Fault detection and recovery for arithmetic circuits with unconventional number representations, - Use of post-CMOS technologies for the implementation of digital circuits at subnanometric integration scale.

Dr. Salvatore Pontarelli has published more than 70 papers on archival Journals and peer-reviewed conferences, and has served as reviewer for many IEEE sponsored journals and conferences. He has been involved in several research projects funded bysuch as: - High-Reliable Programmable Systems for Space Applications, funded by ASI (Italian Space Agency), - PRIvacy-aware Secure Monitoring (PRISM), funded by the European Seventh Framewok Programme (FP7), - Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), funded by the European Cooperation in Science and Technology (COST). In 2011 has been selected to receive an award from the Cisco University Research Program Fund.