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Alexander V. Veidenbaum's talk: "A New Stride Prefetching Approach for Multi-Core Systems Using Global Miss History"

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Introduïda: 06-05-2013
Date: 23/May/2013, 12:00 Room: C6-E101




ABSTRACT

Data prefetching is very important in hiding memory latency and improving performance in both single-core and multicore processors. It is especially important for parallel (multithreaded) applications on multicores using large shared LLCs where single-core prefetchers are often ineffective. This talk presents a new prefetching technique that improves over both stride prefetching and delta-correlation prefetching. The technique identifies strided streams in the LLC miss stream and can detect streams that subsume delta patterns or standard strided streams. This includes identifying streams that subsume individual streams from multiple cores. It also has competitive memory bandwidth requirements in both single-core and multi-core cases. The proposed technique achieves an average speedup of 22% over stride prefetching for SPEComp benchmarks on a four-core system. The average speedup over delta correlation is 7%.

Organizes: Department of Computer Architecture (DAC)


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