Abstract
Over the past decades parallel processor speedup has been an elusive quantity for a broad class of applications. Yet with the end of performance scaling for single processors the need for speedup has never been greater. The problem is not technology but programming models.

One answer to this speedup problem is to create an idealized data flow machine that exactly corresponds to the application and stream data through the resulting machine. This approach can be emulated with FPGAs, providing more than an order of magnitude speedup even as executed as an emulation of the data flow machine

Biography
Michael Flynn is well known for early work on parallel processing. He directed the Architecture and Arithmetic group at Stanford University for more than 20 years where he is now Emeritus Professor of Electrical Engineering. He is also Chairman of Maxeler Technologies, a UK and US based company dedicated to maximum performance computing. He is a fellow of the IEEE and the ACM.

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