ABSTRACT
The primary concern in future architectures is power/energy efficiency. Full-custom design of application-specific IPs can yield up to three orders of magnitude better power efficiency over conventional general-purpose cores. The high-energy cost of a data fetch from memory is an obvious constraint towards an energy efficient design. Therefore, algorithms with efficient implementations must have very high compute intensity (actual floating-point operations per memory read). However, a tremendous design effort is required in integrating a new accelerator for each new application.

In this talk, I present the first steps towards the design of an accelerator that maintains the efficiency of full custom hardware while providing enough flexibility to execute a whole class of coarse-grain compute intensive operations.

I introduce the Linear Algebra Processor (LAP) architecture and further verify that this architecture can perform a broad range of dense linear algebra operations as complex as matrix factorizations, Fast Fourier Transforms (FFTs), and Convolutional Neural Network (CNN) while maintaining ASIC level efficiency. Such process requires expertise and careful codesign of the algorithms and the architecture.

I present a power-performance model that compares state-of-the-art CPUs and GPUs with our design and reveals the sources of inefficiencies. When compared to other conventional architectures for linear algebra applications and FFT, our LAP is over an order of magnitude better in terms of power efficiency. Based on our estimations, up to 55 and 25 GFLOPS/W single- and double-precision efficiencies are achievable on a single chip in standard 45nm technology.

Conference Information