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Conferencia: "Hardware Transactional Memory in the wild - the first year"

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Introducida: 06-05-2014
HPC (CAP) research group invites you to attend the talk.
Speaker: Konrad Lai
Date: Tue, 20/May/2014, 12:00
Room: C6-E106
ABSTRACT
In June 2013, Intel Haswell CPU with support for Intel Transactional Synchronization Extension becomes generally available - 20 years after the publication of the paper on Hardware Transactional Memory. This talk will discuss the results and learning by various researchers around the world using Intel TSX in the first year.

BIOGRAPHY
Konrad Lai retired from Intel in 2013. His last project involved the development of Intel TSX technology.During his 35 years at Intel, he has been involved in microcode, validation, in-order and out-of-order microarchitecture, cache coherent, multiprocessor and fault tolerant system architecture, on-die/on-package cache architecture, SRAM/DRAM/novel memory technology, bus, packaging, and high speed signaling for the i-APX-432, i960, and P6 families. In between, he was in the Intel Labs for 10 years leading a team in microarchitecture research. He has been the Intel liaison to architecture research community for the more than 20 years. Konrad has a BSEE from Princeton University and MSEE from Carnegie Mellon University.

Conference information


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